Physical Design Engineer Jobs in San Carlos, CA

L&T Technology Services - Sunnyvale, CA, United States

As part of the block level implementation, you will need to ensure the floorplan is optimal, congestion issues are resolved, and timing...

from: linkedin.com - 10 days ago

Ursus, Inc. - San Jose, CA, United States

STA Physical Design Engineer LOCATION : San Jose, CA (hybrid 3 days onsite) DURATION: 6+ Months Description: Perform static timing analysis (STA) and timing optimization, generate and verifies timing

from: linkedin.com (+1 source) - 10 days ago

Ursus, Inc. - Menlo Park, California

JOB TITLE: Silicon Physical Design Engineer II - AR/VR LOCATION: 100% Remote, PST Preferred DURATION: 8 month contract PAY RANGE: $64-$70/hr TOP 3 SKILLS: 5 years of relevant analog mixed signal

from: resume-library.com - 9 days ago

Intellectt Inc - Sunnyvale, CA, United States

Job description and if interested kindly do share your resume at rajitha@intellectt.com Job Title: Physical Design Engineer Location: Sunnyvale, CA Job Duties: 10+ years of hands-on experience for block level

from: linkedin.com (+1 source) - 15 days ago

Intellectt Inc - Sunnyvale, CA, United States

Job Title: Physical Design Engineer Location: Sunnyvale, CA Job Description: 10+ years of hands-on experience for block level implementation activities (Netlist to GDS II and Signoff). Experience

from: linkedin.com - 16 days ago

quadric.io, Inc - Burlingame, California

Quadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and...

from: resume-library.com (+1 source) - 14 days ago

Intelliswift Software - Burlingame, CA, United States

, RDC, Synthesis, STA, Power). Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them

from: linkedin.com - 28 days ago

ACL Digital - San Jose, CA, United States

Position: Physical Design Engineer Location: San Jose, CA / Austin, TX Job Description: Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks

from: linkedin.com - 29 days ago

Mindlance - Sunnyvale, California

with Physical Design Engineers and provide them with timing/congestion feedback. Minimum qualifications 10+ Years of experience in backend implementation such as synthesis, timing closure, power analysis etc

from: resume-library.com - 12 days ago

R2 Semiconductor, Inc. - Palo Alto, CA, United States

10nm. The Senior Analog CAD Engineer will be responsible to solve design flow issues from analog mixed signal front-end simulation to physical verification and tape out. The Company is developing power

from: linkedin.com - 13 days ago