25 Asic Verification Engineer Jobs in Santa Clara, CA - page 2
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ASIC Failure Analysis Engineer(has Failure Analysis experience in 7nm (nanometer) semiconductor manu Diverse Lynx - San Jose, California Duration: Fulltime Job Description: Job Title ASIC Failure Analysis Engineer Skill EIS : ASIC Frontend Verification Skill Type Marketable Minimum Experience 8 - 15 Years Qualification BACHELOR OF COMPUTER Yesterday
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Design Verification Engineer Theery - San Jose, CA, United States projects. Position Overview: As a Design Verification Engineer, you will play a crucial role in ensuring the functional correctness and quality of our ASIC designs. You will be responsible for developing 12 days ago
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IC Power Management Design Engineer AmberSemi™ - Dublin, CA, United States experience using Cadence tools, design methodologies, verification flows to tape-out and silicon characterization/testing Proven track record and demonstrated experience in taking mixed signal ASICs Yesterday
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Senior Verification engineer Two95 International Inc. - Sunnyvale, California Hi, Title: Lead / Senior Verification engineer Location: San Jose, CA / Santa Clara, CA Duration: 6+ Months Rate: $Open Skills: UVM and System Verilog Requirement:. • 5+ or more years of proven 12 days ago
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Senior Design Verification Engineer USA Tech Recruitment - San Jose, CA, United States Senior ASIC Verification Engineer | AI Start-up | AI interference Solutions / Autonomous Driving | San Jose Are you a Senior-level Verification Engineer with experience or looking to work 18 days ago
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CPU Design Verification Engineer Prodapt ASIC services (Formerly Innovative Logic) - Mountain View, CA, United States design center (ODC) or staff augmentation. We're seeking a CPU Design Verification Engineer with a strong background in UVM-based verification and experience in working with complex ARM/RISCV/x86 CPU based 18 days ago
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Design Verification Engineer at San Jose CA Mirafra Inc - San Jose, CA simulations and work with design engineers to verify fixes. Write diagnostics for validation of FPGA prototype (pre-tapeout) and ASIC. Replicate silicon bugs in simulation environments and validate fixes or SW Depends on Experience 7 days ago
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Hardware Engineering and R&D - Silicon Verification Engineer 5 Silicon Verification Engineer 5 HireTalent - Mountain View, California then we will have to reconsider. Hardware engineers- will have systems knowledge but not have C or C++ Skill set: " SystemVerilog and C/C++ coding a must " Chip/full system level ASIC Verification skills, and debug skills a must o Yesterday
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ASIC Design Engineer Apple - Cupertino, California, United States Summary Posted: May 15, 2024 Role Number: 200519284 As an ASIC Design Engineer, the individual’s primary responsibility will be RTL design. This will include chip architecture definition, block 9 days ago
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Member of Technical Staff Thermal-Mechanical Engineer Advanced Micro Devices, Inc - San Jose, California or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation 19 days ago
Top locations
- San Jose, CA (11)
- Cupertino, CA (3)
- Mountain View, CA (3)
- Fremont, CA (2)
- Milpitas, CA (2)
- Dublin, CA (1)
- Brentwood, CA (1)
- San Francisco, CA (1)
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