Latest Tool Design Engineer jobs in Livermore, CA

111 Tool Design Engineer Jobs in Livermore, CA

Electrical Engineer Lawrence Livermore National Laboratory - Livermore, CA Laboratories (UL). Software capabilities: Experience using AutoCAD and Revit to prepare design drawings, AGi32 for lighting studies and design, SKM Power Tools, and MS Office Suite. Additional Qualifications USD 142,050.00 - 182,388.00 per year;USD 170,430.00 - 218,868.00 per year 21 days ago
Radar Systems Engineer Lawrence Livermore National Laboratory - Livermore, CA propagation and scattering, radar cross-section estimation and evolution as functions of time and aspect, capable of applying commercial and in-house simulation tools for analysis and design in support USD 132,810.00 per year;USD 170,556.00 ;USD 159,330.00 ;USD 204,636.00 28 days ago
IC Power Management Design Engineer AmberSemi™ - Dublin, CA, United States experience using Cadence tools, design methodologies, verification flows to tape-out and silicon characterization/testing Proven track record and demonstrated experience in taking mixed signal ASICs 5 days ago
OS Kernel Engineer for Semiconductor CPU Scheduling Team in Palo Alto, CA OSI Engineering - Palo Alto, CA, United States team, you will: Learn the tools and processes necessary to become a successful VMKernel engineer and will participate in the design and development of novel operating system techniques and algorithms 2 days ago
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CPU Top-Level Verification Engineer Apple - Santa Clara, CA or SystemVerilog Programming/scripting skills (C, C++, Python)Problem solving skills Description As a CPU top-level design verification engineer owning the verification methodology, tools, and flow of a high USD 170,700.00 - 300,200.00 per year 4 days ago
Senior Hydraulics Design Engineer Hire Score LLC - Fremont, NE, United States in related field 7+ years’ experience as a Mechanical/Design Engineer or 5+ years in hydraulic component design Must be able to communicate effectively in both oral and written responsibilities Experience 10 days ago
Principal Memory Design Engineer/Senior Technical Manager MediaTek - San Jose, CA, United States with comprehensive design verification plans, silicon bring-up plans for high-performance embedded memories. Experience in using industry standard schematic entry tools, advanced transistor level simulators (XA 4 days ago
SoC Power Flow Methodology Engineer Apple - Cupertino, CA are required.Knowledge of Tcl / Perl, experience with EDA tools, GUI development, and/or low-power concepts such as UPF and low-power design is a plus. Description As a Power Flow Methodology Engineer, you'll deliver new USD 138,900.00 - 256,500.00 per year 4 days ago
DevOps CI/CD Verification Engineer - W2 only SPECTRAFORCE - Santa Clara, CA, United States across various hardware platforms. Key Responsibilities: develop, create, modify CI/CD pipelines, and validate SW/HW and/or specialized tools that support the design and development of our world class CPU 4 days ago
Hardware Design Engineer Sedaa Corp - San Jose, CA, United States and design validation. Excellent verbal and written communications skills. Desired Qualifications: Verilog Perl Scripting CAD Tools Job title - Lab Hardware Engineer (Lab Work) Location - San Jose (onsite 5 days ago

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