Latest Design Verification Engineer jobs in Burlingame, CA

90 Design Verification Engineer Jobs in Burlingame, CA

Senior Design Verification Engineer Quadric - Burlingame, CA, United States Quadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadric's co-optimized software and... 30 days ago
Design Verification Engineer Quest Global - Sunnyvale, CA, United States Excellent coding and debugging skills, should have exp. In coding various TB components. Image processing IP verification experience... 3 days ago
Principal/Lead Design Verification Engineer Lightmatter - Mountain View, CA Principal/Lead Design Verification Engineer Lightmatter is a photonic computer company that is redefining what computers and human beings are capable of by building the engines that will drive 2 days ago
CPU Design Verification Engineer Prodapt ASIC services (Formerly Innovative Logic) - Mountain View, CA, United States design center (ODC) or staff augmentation. We're seeking a CPU Design Verification Engineer with a strong background in UVM-based verification and experience in working with complex ARM/RISCV/x86 CPU based 6 days ago
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Design Verification Engineer Net2Source Inc. - Santa Clara, CA, United States – Right Price and acting as a Career Coach to our consultants. Role: Design Verification Engineer Location: Santa Clara, CA -Onsite Duration: Long Term Contract Note: Current role is with our direct client 6 days ago
ASIC Design Verification Engineer Mobiveil Technologies Inc. - Los Altos, CA, US Responsibilities : • Work with RTL designers and software engineers to ensure a high quality design that works first silicon. • Develop detailed test and coverage plans based on the micro 8 days ago
Design Verification Engineer GAC Solutions - Santa Clara, CA, United States Title - Design Verification Engineer Location - Santa Clara, CA (Onsite) Duration - 6+ Months "Desired Qualifications: • Over 7 years of hands-on experience in pre-silicon design verification 6 days ago
Design Verification Engineer Mirafra Technologies - Santa Clara, CA, United States and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM ○ Debug RTL and Gate simulations and work with design engineers to verify fixes. ○ Write diagnostics for validation 11 days ago
Design Verification Engineer EITAcies, Inc. - Santa Clara, CA Drive returned product Failure Analysis, characterizing failures, and escalating issues and trends to the Hardware Quality Engineering... 9 days ago
Design Verification Engineer Capgemini Engineering - Santa Clara, CA, United States We are seeking a Design Verification Engineer with below skills. Total 10 years of experience in UVM based verification. System Verilog assertions experience. Familiarity with C/C++ model integration 14 days ago

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