Verification Engineer Jobs

Quadric - , CA, United States (+1 location)

Quadric is building a full-stack system that is designed to meet the requirements of next-generation edge & edge-cloud computing products...

from: linkedin.com (+1 source) - 2 days ago

USA Tech Recruitment - San Jose, CA, United States

Are you an ASIC Verification Engineer that is on the market for a new opportunity at a highly funded and expanding startup, working on cutting edge projects at the forefront of autonomous driving

from: linkedin.com - 3 days ago

Montage Technology, Inc - Johns Creek, GA, United States

years! Job Description: We are looking for Verification Engineers who will help develop system level UVM test benches for various DDR5 DIMM products, Power Management IC (PMIC) and also CXL 2.0 products

from: linkedin.com - 4 days ago

European Recruitment - San Jose, CA, United States

ASIC Verification Engineer- System Verilog / UVM We are partnered up with a well-established Semiconductor organisation who enable state of the art perception for autonomous vehicles who are looking

from: linkedin.com - 4 days ago

DAC Search Inc - , CA, United States

. We are hiring Design Verifcation Engineers located in Santa, Clara, CA In addition to the description below, key skills for this company are INTERCONNECT, FABRIC, CACHE COHERENCY, NOC'S Hardware Verification

from: linkedin.com - 2 days ago

Combi Packaging Systems LLC - North Canton, OH, United States

While performing the duties of this job, the employee is frequently required to sit at a desk. Standing and walking to different departments...

from: linkedin.com - 4 days ago

Engtal - , TX, United States

and precision. As an FPGA Verification Engineer, you will play a crucial role in ensuring the reliability and efficiency of our FPGA-based trading systems. About the Role: As an FPGA Verification Engineer

from: linkedin.com - 2 days ago

ACL Digital - El Segundo, CA, United States

Role: Sr. UVM Design Verification Engineer (ASIC/FPGA) Location: El Segundo, California (Onsite) Duration: Contract Description: ASIC/FPGA Design Verification Engineer with UVM Experience Must

from: linkedin.com - 4 days ago

SSi People - El Segundo, CA, United States

Required Skills: • 5+ years of experience • 1-2 years of UVM tool • Cadence Xcelium verification tool

from: linkedin.com - 4 days ago

Digital Prospectors - Palo Alto, CA, United States

Position: Senior Software Verification Engineer Location: Palo Alto, CA (Hybrid – 3 days onsite) Length: 12+ months Job Description: Our client is seeking an exceptionally skilled Senior Software

from: linkedin.com - 4 days ago