Asic Verification Engineer Jobs in Santa Clara, CA

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Design Verification Engineer  

Synapse Design Inc. - San Jose, CA, United States

Engineer Location :: San Jose,CA Staff Verification with a some design experience. 8+ years of practical design and verification experience using SystemVerilog UVM and ASIC verification . Experience

from: linkedin.com - 16 days ago

ASIC Engineer, Design Verification  

Meta Platforms, Inc. (f/k/a Facebook, Inc.) - Sunnyvale, CA

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following position in Sunnyvale, CA: ASIC Engineer, Design Verification: Define and implement IP/SoC verification plans, build verification test

from: Dice.com - 11 days ago

Senior HAPS Validation Engineer  

Mirafra Technologies - San Jose, CA, United States

and disaggregated compute ecosystems. You should have prior knowledge about FPGAs and computer architecture. As the FPGA Engineer for the team, you will have the opportunity to work in design verification, debug

from: linkedin.com - 24 days ago

Hardware Verification Engineer  

BrickRed Systems - Mountain View, CA, United States

We are seeking an experienced and highly skilled Silicon Verification Engineer to join our dynamic team. The ideal candidate will have a robust background in ASIC design and verification

from: linkedin.com - 16 days ago

Senior Verification engineer  

Two95 International Inc. - Sunnyvale, California

Hi, Title: Lead / Senior Verification engineer Location: San Jose, CA / Santa Clara, CA Duration: 6+ Months Rate: $Open Skills: UVM and System Verilog Requirement:. • 5+ or more years of proven

Register your RESUME

from: resume-library.com - 6 days ago

CPU Design Verification Engineer  

Prodapt ASIC services (Formerly Innovative Logic) - Mountain View, CA, United States

design center (ODC) or staff augmentation. We're seeking a CPU Design Verification Engineer with a strong background in UVM-based verification and experience in working with complex ARM/RISCV/x86 CPU based

from: linkedin.com - 16 days ago

IC Power Management Design Engineer  

AmberSemi™ - Dublin, CA, United States

experience using Cadence tools, design methodologies, verification flows to tape-out and silicon characterization/testing Proven track record and demonstrated experience in taking mixed signal ASICs

from: linkedin.com - 24 days ago

ASIC and/or FPGA Design & Verification Engineer (Lead, Senior, P  

Boeing Company - Mountain View, CA

. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC and/or FPGA Design and Verification Engineers at Lead, Senior & Principal levels to join us as part of our Boeing Unspecified

from: clearancejobs.com - 26 days ago

Design Verification Engineer At San Jose, CA  

ProIT Inc. - San Jose, CA

Job Title: Design Verification Engineer Locations: San Jose, CA Type of hire: Fulltime/Contract Job Description: Education Requirements BS/MS in EE/CE, plus 7+ years of Design Verification experience

from: Dice.com - 4 days ago

Design Verification Engineer  

Apple - Sunnyvale, California, United States

-power architecture and complex debug architectures, etc. You will have a dedicated/hands-on ASIC DV experience in reusable verification methodology such as UVM or OVM. As a Design Verification Engineer

from: jobs.apple.com - 6 days ago


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