Validation Engineer Jobs in Campbell, CA

Mirafra Technologies - San Jose, CA, United States

Knowledge of RTL logic design (Verilog), strong experience working with FPGAs. Familiarity with PCIe, USB, Ethernet, ARM, and other...

from: linkedin.com - 24 days ago

Mobiveil Technologies Inc. - San Jose, CA, US

· Experience in developing or testing complex high-performance storage systems (HDD or SSD). · In-depth understanding of systems/hardware...

from: jobvertise.com - 2 days ago

Qnovo - Milpitas, CA, United States

Open Role: Software Test Validation Engineer About Qnovo Since 2010, Qnovo has redefined one of the most fundamental technological advances of the last century - the lithium-ion battery. As an early

from: linkedin.com - 21 days ago

Akkodis - San Jose, CA, United States

Akkodis is looking for an ADAS Verification, Validation, and Simulation Engineer - Parking Functions at the San Jose, CA location. Ideally, the ADAS Verification, Validation, and Simulation Engineer

from: linkedin.com - 15 days ago

Eurofins USA Consumer Product Testing - Santa Clara, California

Job Description Work Schedule: 9AM - 3PM, Monday to Friday, 25 hours/week. Responsibilities: Oversee daily activities of test engineers to ensure tests being performed conforms to global standards

from: resume-library.com - 2 days ago

LinkedIn - Mountain View, CA, United States

strategy and investment in their organizations. As a Sr. Staff Software Engineer on the Validation Engineering team, you will be responsible for driving the technical direction and development of cutting

from: linkedin.com - 10 days ago

Akkodis - San Jose, CA, United States

for software development. Will work closely with our validation engineers to support the analysis of measurement data to understand feature performance and root cause analysis while testing the ADAS features

from: linkedin.com - 18 days ago

tanishasystems - Cupertino, CA, US

Experience in using any battery testing tools for embedded battery systems Record and analyze test data, document test findings and...

from: jobvertise.com - 14 days ago

Mirafra Technologies - San Jose, CA, United States

○ Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM ○ Debug RTL and Gate simulations and work with design engineers to verify fixes. ○ Write

from: linkedin.com - 14 days ago

L&T Technology Services - Sunnyvale, CA, United States

Experience / understanding of how performance and event monitors are used in Silicon Job Description:

from: linkedin.com - 29 days ago